Espressif Systems /ESP32-S3 /SENSITIVE /CORE_X_IRAM0_PMS_CONSTRAIN_2

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Interpret as CORE_X_IRAM0_PMS_CONSTRAIN_2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS

Description

corex iram0 permission configuration register 1

Fields

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0

core0/core1’s permission of instruction region0 of SRAM in world1

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1

core0/core1’s permission of instruction region1 of SRAM in world1

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2

core0/core1’s permission of instruction region2 of SRAM in world1

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3

core0/core1’s permission of instruction region3 of SRAM in world1

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0

core0/core1’s permission of icache data sram block0 in world1

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1

core0/core1’s permission of icache data sram block1 in world1

CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS

core0/core1’s permission of rom in world1

Links

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